Non-volatile memory (“NVM”) cells are fabricated in a large variety of structures, including but not limited to Poly-silicon floating gate, as shown in FIG. 2A, and Nitride Read Only Memory (“NROM”), as shown in FIG. 2B As is well known, an NVM cell's state may be defined and determined by its threshold voltage (“Vt”), the gate to source/drain voltage at which the cell begins to significantly conduct current
Different threshold voltage ranges are associated with different logical states, and a NVM cell's threshold voltage level may be correlated to the amount of charge (e g electrons) stored in a charge storage region of the cell. FIG. 1A shows a voltage distribution graph depicting possible threshold voltage distributions of a binary non-volatile memory cell, wherein vertical lines depict boundary voltage values correlated with each of the cell's possible states Cells having Vt Lower than EV level may be said to be erased verified Cells having Vt Higher than PV may be said to be program verified. These two limits define the completion of programming and erase sequences that may be performed on a cell. A Program sequence of programming pulses may be used to drive the Vt of a cell higher than PV, while an erase sequence may drive the cell's Vt lower than EV. Also visible in FIG. 1A are vertical lines designating a Read Verify (RV) level and an Intermediate Program Verify voltage, PV1, designating the start of regions before the Program Verify threshold
FIG. 1B shows a voltage distribution graph depicting possible threshold voltage distributions in the charge storage region of a multi-level non-volatile memory cell (“MLC”), wherein one set of vertical lines depict boundary values correlated with each of the cell's possible Program Verify Threshold Voltages (PV00, PV01, etc), another set of vertical lines depict boundary values correlated with the Read Verify level of each of the cell's possible Program states (RV00, RV01, etc), and yet another set depict boundary lines for Intermediate Program Verify voltages (PV100, PV101, etc.) associated with each of the states
The amount of charge stored in a charge storage region of an NVM cell, may be increased by applying one or more programming pulses to the cell. While the amount of charge in the cell may decrease by applying an erase pulse to the NVM cell which may force the charge reduction in the cell's charge storage region, and consequently may decrease the NVM's threshold is voltage
A simple method used for operating NVM cells (e.g. programming, reading, and erasing) uses one or more reference structures such as reference cells to generate the reference levels (i.e. PVs, EVs) Each of the one or more reference structures may be compared against a memory cell being operated in order to determine a condition or state of the memory cell being operated. Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's threshold level is compared to that of a reference structure whose threshold level is preset and known to be at a voltage level associated with the specific state being tested for Comparing the threshold voltage of an NVM cell to that of a reference cell is often accomplished using a sense amplifier. Various techniques for comparing an NVM's threshold voltage against those of one or more reference cells, in order to determine the state(s) of the NVM's cells, are well known
When programming an NVM cell to a desired state, a reference cell with a threshold voltage set at a voltage level defined as a “program verify” level for the given state may be compared to the threshold voltage of the cell being programmed in order to determine whether a charge storage area or region of the cell being programmed has been sufficiently charged so as to be considered “programmed” at the desired state If after a programming pulse has been applied to a cell, it has been determined that a cell has not been sufficiently charged in order for its threshold voltage to be at or above a “program verify” level (i e the threshold voltage of the relevant reference cell) associated with the target program state, the cell is typically hit with another programming pulse to try to inject more charge into its charge storage region Once a cell's threshold value reaches or exceeds the “program verify” level to which it is being programmed, no further programming pulse should be applied to the cell
Groups or sets of cells within an NVM array may be programmed and/or erased concurrently The group or set of NVM cells may consist of cells being programmed to (or erased from) the same logical state, or may consist of cells being programmed to (or erased from) each of several possible states, such as may be the case with MLC arrays. Since not all cells have the same susceptibility to being programmed and/or being erased, cells within a set of cells receiving programming or erasing pulses may not program or erase at the same rate Some cells may reach a target program state, or an erased state, before other cells in the same set of cells that are receiving programming or erasing pulses concurrently
A further issue associated with the erasure of one or more NVM cells within a set of cells being erased, is that channel current invoked during NVM (e g NROM) cell erasure using constant voltages pulses is characterized by a high peak, which quickly subsides (See FIG. 3). The cause of such a channel current profile is carriers created by band-to-band tunneling at the surface of the deeply depleted drain junction (associated with Gate Induce Drain Leakage) More specifically, in a NVM cell, including but not limited to NROM cells, carries may be injected into the gate dielectric stack (or floating gate, if such exists), thereby reducing the vertical electric field which facilitates current flow and causing the current to subside, as evident from the current graph of FIG. 3.
One of the drawbacks of such a channel current profile during erasure is that the channel current peak in each of the NVM cells being erased limits the amount of cells that can be erased simultaneously, either due to current consumption limits imposed on memory product and/or due to limitations on the circuits implemented in the NVM product (e.g. charge pump failures) Furthermore, the efficiency of the constant voltage erase pulse also subsides with time, as is evident from the graphs in FIG. 4, which FIG. 4 shows the reduction of channel current, along with the reduction of the highest threshold voltage, within an NVM array population receiving a 3 ms constant voltage erase pulse as a function of time As evident from FIG. 4, both the channel current and the rate of the downward threshold voltage shift subsides shortly after the beginning of the erasure pulse and the erasure process becomes significantly less efficient during the latter portion of the pulse (i.e. current continues flowing −04 mA in this example, yet the threshold voltage is downward shift is very slow)
Although during the second half of a constant voltage erase pulse a current may still flow through the cells, erasure of the cells becomes very slow and weak Thus, the result of a channel current profile associated with a constant voltage erase pulse is, (1) relatively large current consumption during cell erasure, and (2) erasure inefficiency. These two drawbacks translate into reduced erase rates in many NVM (e g NROM) memory product (or any other memory technology incorporating tunnel assisted hot carrier injection), also reducing the number of cells which can be erased simultaneously and requiring that the duration of erase pulses be sufficiently long to compensate for erasure inefficiency By comparison, whereas a typical programming pulse may have a duration of several hundred nanoseconds, a typical erase pulse may have a duration of several microseconds.
There is a need in the field of NVM production for improved methods, circuits and systems of erasing one or more NVM cells.